A fundamental consideration for electronic circuits is the interconnection of elements of the circuit. A typical prior art interconnection technology is a printed circuit board (PCB), where conductive traces are printed on a laminate and various components are mounted on the PCB to provide electrical interconnections. One fundamental consideration is that while new generations of integrated circuits continue to offer finer and finer fabrication linewidths (currently on the order of 50 nm), printed circuit board linewidths have remained on the order of 5 mil spacing (˜125 u), a factor of 2,500 coarser than integrated circuit linewidths. Accordingly, chip design practice continues to maximize the complexity and functionality of the chip, and minimize the number of input/output (I/O) lines leaving the chip. For chip designs with a large number of I/O connections, adapting the chip I/O pins to the PCB remains an unsolved problem, as chip feature sizes continue to shrink and PCB linewidths have remained unchanged.
FIG. 1A shows a side view of a Ball Grid Array (BGA) package 101 which has been soldered to a printed circuit board 102 having a series of pads which electrically connect to the balls 114 of the BGA package 101. The BGA package 101 comprises the chip 104 which is mounted to a substrate 112 with printed wire bonding pads 110 on top and electrical traces to BGA pads 115 below. Individual wires 108 are bonded, such as by ultrasonic welding, from the pads 106 of the IC 104 to the bonding pads 110 of the substrate 112. The chip 104 may be mechanically attached to the substrate 112 using an adhesive or other technique, with the pads 106 accessible from the top, as shown. After wire bonding of the interconnect wires 108 between the chip 104 pads and substrate 112 pads 110, a sealant 105 such as epoxy is applied to protect the top of the chip. In a secondary operation, individual balls 114 are attached to the bottom pads of the substrate 112 at each attachment point 115, so that during a subsequent operation, they reflow at elevated temperature to form electrical connections to circuit board 102. The substrate 112 may be a conventional printed circuit board which follows typical PCB linewidths of 5 mil (˜125 u) wide and 5 mil (˜125 u) edge spacing, formed using printed copper traces with a nickel flash or other thin plating over the traces for material compatibility with the die bond wires 108, which may be aluminum, gold, silver, or copper. In a prior art integrated circuit, individual devices are formed into a chip substrate such as silicon (Si) by patterned localized ion implantation to achieve doping to form semiconductor devices, and the semiconductor devices are interconnected using a series of metallic interconnects (metallization layers) formed from aluminum or copper, and optional intervening insulating or barrier layers. The chip interconnect lands (or pads) are typically provided using the same material as the layer metallization, usually using aluminum for low complexity/density chips and copper for high complexity/density chips.
FIG. 1B shows a top view of FIG. 1A, with structures identified using the reference numbers of FIG. 1A, as is done throughout the present patent application.
The prior art system of FIG. 1A is limited by the PCB linewidths which are significantly coarser than the chip linewidths. Additionally, the wire bonding method of FIG. 1A introduces undesirable lead inductance from chip 104 to PCB 102 which limits the high frequency signal propagation ability of the resulting circuit. While it is possible to maintain the high frequency transmission line characteristics of a printed circuit board trace using a reference ground plane, it is not possible to provide such continuous impedance or a continuous ground reference for a bond wire such as 108 which is also inductively coupled to other bond wires, particularly as the switching frequency delivered to the transmission line increases.
One consideration of PCB technology is manufacturability and serviceability, including replacement of individual devices if they are discovered to be defective. In the BGA packaging technology of FIG. 1A, when a chip is defective, localized heat may be applied to the 101 BGA chip assembly until the BGA balls between circuit substrate 112 and PCB 102 melt, after which the BGA chip assembly 101 is removed, and a replacement BGA chip assembly 101 may be installed. Additionally, for high value BGA assemblies 101, it is possible to re-ball (install new solder balls 114) and reattach the BGA package 101 to the PCB 102 using localized heating and solder flux until the balls 114 melt (reflow) onto the pads on adjacent upper and lower surfaces.
To address the low package density and lead inductance of BGA packaging, a “flip chip” packaging method shown in FIG. 2A incorporates an inverted chip substrate 202, with the chip circuits and lands facing downwards compared to the up-facing chip land orientation of the BGA chip package of FIG. 1A. In the flip chip approach, a chip 202 has interconnect lands formed on the bottom surface (typically in copper), and an insulating mask layer 204 prevents migration of the solder balls 208 and electrically isolates the adjacent interconnect layer. Flip chip interconnects involve comparatively high tooling costs and capital equipment costs, and so are commonly used in high volume and high density packaging methods, such as consumer cell phones. FIG. 2B shows the bottom view of a flip chip for comparison with the side view of FIG. 2A.
One problem of the prior art is that BGA chip bonding introduces lead inductance, which is solved in the flip chip method at the expense of high tooling cost and the difficulty of reworking or removing a flip-chip device. Another problem of the prior art packaging is that it may be desired to integrate several chips and circuits onto a PCB for use in an agency-regulated assembly, where the chip module is inspected and certified by a regulatory agency. Examples of such agency-regulated assemblies include Bluetooth® or 802.11 Wireless Local Area Network (WLAN) module where a regulatory agency inspects the module for RF emissions against a published standard, and certifies the module as compliant to that emissions standard. Use of a pre-approved module in this form allows the user of the module to make changes in their interconnected PCB design without the requirement for re-certification, which would be otherwise required if the previously approved design in the pre-approved module were incorporated into their PCB.
The inventors have discovered a high density packaging apparatus and method which provides several factors of finer PCB linewidth than provided by prior art PCB fabrication methods, with minimal incremental tooling cost. Accordingly, is desired to provide a packaging method which enables direct mounting of integrated circuit chips to a circuit board or substrate for low volume cost-sensitive applications, and which provides continuous electrical connections for high speed operation and improved signal integrity, and without inductive wire bonding of the prior art.